Manufacturing process and temperature variations are the cause of variation of characteristics of various devices on a semiconductor chip. For example, memory bitcells of different memory dies of a single wafer may have memory bitcell die-to-die corner variation across the wafer. Currently, monitoring temperature variations and a few process variations of memory dies are performed using logic cells that are created using a separate mask layer than the memory bitcells. For example, one or more assist circuitries implemented using logic cells may receive temperature variations information from a temperature monitor and limited process corners from existing process monitors and provide an adaptive improvement mechanism for memory characteristics such as VCCmin, leakage, and other memory characteristics.
The existing logic cell monitors, however, are not able to track bitcell process variations, and more specifically, are not capable of identifying the worst case N and P skewed corners for bitcells. The N and P skewed corners are the process corners that N and P devices have most skewed characteristics. For example, a SF corner, which represents a slow N-device and a fast P-device, and a FS corner, which represents a fast N-device and a slow P-device are the worst case process corners for 6T-bitcells (e.g., memory bitcells having six transistors), and are not distinguishable by the existing logic cell monitors. Further, the existing logic cell monitors do not work for all temperatures or low supply voltages.